1. Field of the Invention
The present invention relates to the fabrication of integrated circuits and, more particularly, to the field of polishing and planarizing semiconductor wafers.
2. Description of the Related Art
This section is intended to introduce the reader to various aspects of art which may be related to various aspects of the present invention which are described and/or claimed below. This discussion is believed to be helpful in providing the reader with background information to facilitate a better understanding of the various aspects of the present invention. Accordingly, it should be understood that these statements are to be read in this light, and not as admissions of prior art.
Integrated circuits are generally mass produced by fabricating thousands of identical circuit patterns on a single semiconductor wafer and subsequently divided them into identical die or chips. Semiconductor wafers are generally made of silicon. To produce the integrated circuit many commonly known processes are used to modify, remove, and deposit material onto the semiconductor wafer. Processes such as ion implantation, sputtering, etching, chemical vapor deposition and variations thereof, such as plasma enhanced chemical vapor deposition, are among those commonly used. These processes are often selectively applied to an integrated circuit through the use of a masking process In the masking process, a photomask containing the pattern of the structure to be fabricated is created, and the wafer is coated with a light sensitive material called photoresist. Then the resist-coated wafer is exposed to ultraviolet light through a photomask to soften or harden parts of the resist depending on whether positive or negative resist is used. Once the softened parts of the resist are removed, the wafer is treated by one of the processes as discussed above to modify, remove, or replace the part unprotected by the resist, and then the remaining resist is stripped. The masking process permits specific areas of the integrated circuit to be modified, removed, or replaced.
These steps of deposition or removal are frequently followed by a planarization step such as chemical mechanical planarization (CMP). Generally speaking, planarization is a process of removing material to render a surface smooth. CMP is the process of smoothing and planing aided by chemical and mechanical forces. The planarization process helps to minimize barriers to multilayer formation and metallization, as well as to smooth, flatten, and clean the surface. This process involves chemically etching a surface while also mechanically polishing it. The combined action of surface chemical reaction and mechanical polishing allows for controlled, layer-by-layer removal of the desired material from the wafer surface resulting in the preferential removal of protruding surface topography and producing a planarized wafer surface. In the past few years, CMP has become one of the most effective techniques for planarizing a semiconductor wafer.
In general, the CMP process involves holding a semiconductor substrate, such as a wafer against a rotating wetted polishing pad under controlled downward pressure. Alternately, the CMP process may involve holding a wetted polishing pad while rotating a semiconductor substrate, such as a wafer, under controlled downward pressure. A polishing slurry deposited onto the polishing pad contains etchants and an abrasive material such as alumina or silica. A rotating wafer carrier is typically utilized to hold the wafer under controlled pressure against a polishing pad. The polishing pad is typically made up of a soft material such as felt fabric impregnated with blown polyurethane.
The CMP process consists of moving a sample surface to be polished against a pad that is used to provide support against the sample surface, and providing slurry between a sample surface and pad to effect the polishing leading to planarization. Abrasive particles in the slurry cause mechanical damage on the sample surface, loosening the material for enhanced chemical attack or fracturing off the pieces of surface into a slurry where they dissolve or are swept away. The process is tailored to provide enhanced material removal rate with high points on surfaces, thus affecting the planarization. Note that chemistry alone typically will not achieve planarization because most chemical actions are isotopic. Mechanical grinding alone, theoretically, may achieve the desired planarization but is generally not desirable because of the extensive associated damage of the material surfaces.
As described above, the three key elements in the CMP process include the surface to be polished, the pad which enables the transfer of mechanical forces to the surface being polished, and the slurry which provides both chemical and mechanical effects. The term pad is used loosely to refer to any soft material which assists in material removal. One such pad is a polishing web. A polishing web is generally a continuous roll of material which is fed through a series of rollers on a CMP system. The web is fed across a table with a solid support surface where a rotating wafer carrier applies the downward mechanical force against the web in order to facilitated the polishing of the wafer. As a wafer is planarized, material is removed from the wafer and deposited onto the web. Before the next wafer is processed, the excess material deposited by the previous wafer should be removed from the web.
Currently, to clean the web between each planarization cycle, the web must be advanced from the polishing area and treated with a cleaning agent. To advance the web, the rollers on the CMP system must be rotated. If the rollers are advanced forward to facilitate the cleaning process, new webbing, previously unexposed because of its positioning on the web roll, will be exposed to possible contamination. Once the roll is retracted to its original position after the cleaning process, the contaminated portion of the web is rolled into the unexposed roll thereby introducing contaminants to previously unexposed portions of the web roll.
The present invention may address one or more of the problems set forth above.